1. Field of the Invention
The present invention relates to a high frequency power amplifier having a pluralty of amplifying systems and a wireless communication apparatus including the high frequency power amplifier, and particularly relates to a technology usefully applicable to a multi-band communication type of cellular phone which has multiple communication functions of different communication frequencies.
2. Prior Art
In North American cellular phone market, so-called dual mode cellular phones have recently been spreading which are cellular phones incorporating conventional analog AMPS (advanced mobile phone services) that cover the whole of the North America and digital services such as TDMA (time division multiple access) and CDMA (code division multiple access).
In other regions including Europe, GSM (Global system for mobile communication and DCS (digital cellular system) utilizing TDMA techniques and FDD (frequency division duplex) techniques are used.
In xe2x80x9cNikkei Electronicsxe2x80x9d pp. 140-153 published by Nikkei BP Corp. on Jul. 26, 1999 [No. 748], a dual mode cellular phone was disclosed in which a GSM having an operating frequency of 800 to 900 MHz and a DCS having an operating frequency of 1.7 to 1.8 GHz are integrated. The same article disclosed a multi-layer ceramics device in which passive components are integrated to make the circuit as a whole compact.
Further, a dual band RF power module was disclosed in xe2x80x9cGAINxe2x80x9d No. 131, January 2000 published by Semiconductor Group of Hitachi, Ltd.
There is a trend toward cellular phones with increased functions to allow advanced information communication. High frequency power amplifiers (high frequency power amplifier modules) incorporated in cellular phones have more functions to satisfy such a need. Especially, high frequency power amplifiers having a plurality of communication modes (and communication bands) are assembled from a greater number of components compared to single communication mode products, which increases the size and cost of such devices.
Under such circumstances, the inventors studied the possibility of a reduction in the number of chip resistors incorporated in a high frequency power amplifier in order to provide the amplifier with smaller outline dimensions.
FIG. 23 is a circuit diagram showing the relationship between an equivalent circuit of a conventional dual band type high frequency power amplifier module incorporating a GSM and a DCS and semiconductor chips and the like. The high frequency power amplifier module has an amplifying system e for GSM as a first amplifying system and an amplifying system f for DCS as a second amplifying system.
The GSM amplifying system e has a three-stage consisting configuration (consisting of a first amplifying stage, a second amplifying stage, and a third amplifying stage (final amplifying stage)) in which transistors Q1, Q2, and Q3 are sequentially cascaded between an input terminal Pin-GSM and an output terminal Pout-GSM.
Each of the transistors Q1, Q2 and Q3 is constituted by a MOSFET (metal oxide semiconductor field-effect-transistors) and is applied with a signal and a bias potential at its gate electrode which is a control terminal. The bias potential is applied to a bias terminal Vapc-GSM (or automatic power control terminal), and a predetermined bias potential is applied to the respective control terminal through bias resistors R1 through R5.
A power supply potential Vdd-GSM is applied to a first terminal (drain terminal) of each of the transistors Q1, Q2, and Q3, and an amplification signal is output to the first terminal. A reference potential (ground potential) is supplied to a second terminal (source electrode) of the transistors. L1 through L7 represent a matching circuit.
The DCS amplifying system f has the same configuration as that of the above-described GSM amplifying system e. Specifically, it has a three-stage configuration (consisting of a first amplifying stage, a second amplifying stage, and a third amplifying stage (final amplifying stage)) in which transistors Q4, Q5, and Q6 are sequentially cascaded between an input terminal Pin-DCS and an out put terminal Pout-DCS.
Each of the transistors Q4, Q5 and Q6 is constituted by a MOSFET and is applied with a signal and a bias potential at its gate electrode which is a control terminal. The bias potential is applied to a bias terminal Vapc-DCS, and a predetermined bias potential is applied to the respective control terminal through bias resistors R6 through R10.
A power supply potential Vdd-DCS is applied to a first terminal (drain terminal) of each of the transistors Q4, Q5, and Q6, and an amplification signal is output to the first terminal. A reference potential (ground potential) is supplied to a second terminal (source electrode) of the transistors. L8 through L14 represent a matching circuit.
The transistors Q1 and Q2 of the GSM amplifying system e and DCS amplifying system f have a monolithic configuration in that they are incorporated in a single semiconductor chip. In such a configuration, however, bias resistors are externally mounted, which hinders reduction of the size of high frequency power amplifiers. Further, while the first and second amplifying stages of both the GSM amplifying system e and DCS amplifying system f are integrated in one semiconductor chip, two semiconductor chips are required because there are two amplifying systems, which also hinders reduction of the size of high frequency power amplifiers.
Referring to the transistors that constitute the amplifying stage, since the threshold voltage Vth of the transistors is slightly inconsistent (varies) between production lots, the bias resistance ratios of the resistors that form a bias circuit must be changed from lot to lot. This method makes manufacturing operations complicated because chip resistors must be selected for use in each production lot.
It is an object of the invention to provide a compact high frequency power amplifier and a wireless communication apparatus incorporating the same high frequency power amplifier.
It is another object of the invention to provide a technique for allowing a bias resistance ratio to be easily adjusted in accordance with a change in a threshold voltage Vth of a transistor.
The above and other objects and novel features of the invention will become apparent from the description of the present specification and the accompanying drawings.
Briefly, primary aspects of the invention disclosed in this specification are as follows.
(1) There is provided a high frequency power
amplifier having a plurality of amplifying systems, characterized in that each of the amplifying systems comprises:
an input terminal to which a signal to be amplified is supplied;
an output terminal;
a bias terminal;
a plurality of amplifying stages which are sequentially cascaded between the input terminal and output terminal; and
a bias circuit connected to the bias terminal and each of the amplifying stages to apply a bias potential to the amplifying stage, in that each of the amplifying stages includes a control terminal for receiving an input signal and the bias potential supplied to the stage and a first terminal for transmitting an output signal of the stage, and in that a first amplifying stage and a second amplifying stage of each of the amplifying systems are monolithically formed on a single semiconductor chip, and a part of bias resistors that constitute bias circuits of the first amplifying stage and second amplifying stage are monolithically formed on the semiconductor chip.
Referring to the terminals of the first amplifying stage and second amplifying stage provided on a surface of the semiconductor chip, the control terminals and the first terminals are alternately provided in the same direction.
A wire that is connected to the control terminal of the second amplifying stage provided on the surface of the semiconductor chip and a wire connected to the first terminal of the second amplifying stage extend in directions orthogonal to each other or in directions crossing each other.
The bias resistance ratio of the first amplifying stage of each of the amplifying systems or the bias resistance ratios of the first amplifying stage and second amplifying stage can be adjusted. Specifically, the bias resistance ratio of the first amplifying stage or the bias resistance ratios of the first amplifying stage and second amplifying stage are adjusted by selecting connecting positions of electrical connectors that connect the plurality of bias resistors formed on the surface of the semiconductor chip, the choice including no connection with the electrical connectors.
Such a high frequency power amplifier is incorporated in a wireless communication apparatus to allow dual band communication.
With the means as described in the above (1), (a) since the first amplifying stage and second amplifying stage of each amplifying system are monolithically formed on a single semiconductor chip, a compact size can be achieve compared to a structure in which they are incorporated in separate semiconductor chips. Since a part of bias resistors that constitute bias circuits for the first amplifying stage and second amplifying stage are monolithically formed on the semiconductor chip, the high frequency power amplifier can be made compact compared to a structure in which chip resistors are separately mounted.
(b) The size and manufacturing cost of the high frequency power amplifier can be reduced through a reduction in the number of components that is achieved by monolithically forming the first amplifying stage and second amplifying stage of each amplifying system on a single semiconductor chip and by monolithically forming a part of bias resistors that constitute bias circuits for the first amplifying stage and second amplifying stage on the semiconductor chip as described in the above (1).
(c) Referring to the terminals of the first amplifying stage and second amplifying stage provided on a surface of the semiconductor chip, control terminals (e.g., gate electrodes) and first terminals (e.g., drain electrodes) are alternately provided in the same direction. Therefore, the direction of extracting the output of the first amplifying stage (the extending direction of the wire) and the direction of extracting the output of the second amplifying stage (the extending direction of the wire) are not close and adjacent to each other, which makes it possible to prevent any reduction in the gain and isolation attributable to a mutual induction effect between the wires.
(d) Since the input wire connected to the control terminal of the second amplifying stage provided on the surface of the semiconductor chip and the output wire connected to the first terminal of the second amplifying stage extend in directions orthogonal to each other or in directions crossing each other, it is possible to suppress crosstalk between them.
(e) A predetermined bias resistance ratio can be achieved by setting a bonding program for the threshold voltage Vth of each transistor and by connecting predetermined bias resistors with the electrical connectors (bonding wires) based on the set program (there is an alternative of providing no connection with the electrical connectors). The resistance of a bias resistor constituted by a conductive layer formed on a semiconductor chip can be defined with accuracy of 5% or less. It is therefore possible to set an optimum bias potential for each transistor to stabilize the operating point of the transistor. As a result, variations of a power control curve (Vapc-Pout) can be reduced to provide improved characteristics.
(f) A wireless communication apparatus incorporating a high frequency power amplifier having the advantages described in the above (a) through (e) is capable of high performance dual band communication and can be provided at a low cost with a compact size.